Thomas A. Amberg
ta (at) taweb (dot) com
www.taweb.com
(408) 691-4276
Sunnyvale, CA

Summary

I am a Semiconductor Design Engineer & Software Designer with a proven record of successful tape-outs and working tools. My interests are in creating leading-edge designs that are profitable, maintainable, and enjoyable to use.

Education + B.S. Electrical Engineering; Michigan Technological University, 1992;
        Houghton, MI 49931; Option: Computer Engineering
+ GM Knowledge Engineering Apprenticeship Program
+ Cal Tech Course on VLSI design, taught by Carver Mead (Audited)
+ Cadence training on Virtuoso, SOC Encounter, SKILL, DRACULA, IC Craftsman, and SE
+ Synopsys training on PrimeTime

Computer Languages & Electronic Design Tools
C / C++ / Objective-C
Verilog and VHDL
Perl
tcl (for Encounter and Magma)
SPICE
SKILL (LISP)
HTML / JavaScript
Some PHP
CAD Tools I have used for design, built flows around, or developed first hand:
  • Cadence: Virtuoso in both DF2 (5.141) & OpenAccess (6.1) environments,
        SOC Encounter (First Encounter) / Nanoroute (both raw and in "Foundation Flow"), IC Craftsman (ICC), Silicon Ensemble (SE)
        Assura Physical Verification, Dracula
        Fire & Ice (Parasitic Extraction), VoltageStorm & ElectronStorm
  • Synopsis: Hercules DRC, LVS, and RCX, StarRC, Railmill, and PrimeTime
  • Mentor Graphics: Calibre LVS, DRC, PEX (xCalibre)
  • IBM EDA tools: ChipBench, ChipEdit, EinsTimer, Niagara DRC/LVS
  • TannerEDA: L-Edit Layout, DRC, LVS, and Extraction
  • Magma: Talus
  • Revision Control Systems: Cliosoft SOS, CVS, RCS, IBM internal system, Syncronicity

Qualification & Experience

Independent IC Design & Software Consultant
1-10 to present

Self Employed, Sunnyvale CA, Denver CO, and Leuven Belgium. Clients included:
+ Arrow Electronics Custom Logic Solutions (Denver, CO) ARM-based SOC hierarchical P&R / timing closure (SOC Encounter);
+ Uniquify (Santa Clara, CA) Physical Verification and EDA tool consultant of low-power SOCs;
+ Magwel (at IMEC, Leuven, Belgium) Created 3-D electromagnetic simulation-related tools;
+ Completed official Synopsys PrimeTime training and working on FPGA synthesis project;

Mixed Signal Physical Design Engineer
5-08 to 6-24-09
(left due to large layoff)

Invisage Technologies, Inc.; Menlo Park, CA;

Physical design & verification engineer for a start-up's complex mixed signal imager chip;

+ Successful initial tape-out of chip using a custom foundry process (to support InVisage's QuantumFilm process):
- bring-up & daily driving of SOC Encounter for P&R (created all control scripts);
- extensive review & correction of technology files from our foundry partner;
- wrote & drove Virtuoso tools for floorplanning, analysis, and automating analog design;
- designed power grid and performed IR Drop and current density analysis;
- designed the IO Ring;
- created specialty Assura DRC and LVS decks for various layout debugging tasks;

+ Successful post-silicon metal-spin ECO to implement an ADC bus raw-data bypass;

+ Extensive product definition chip floorplanning;

+ Resident CAD tools expert:
- migrated the digital design flow from DF2 & LEF/DEF to Open Access (Virtuoso 6.1);
- debugged many various and sundry CAD tool problems for users;
- was creating hierarchical and automated chip implementation flow;

+ Managed disk space across servers, writing analysis tools to monitor database growth;

+ Resident "plotmeister" and chip photographer (macro photography);

+ Work done in SOC Encounter, Virtuoso, Assura, SKILL, tcl, and Perl.

Independent IC Design Consultant & Software Developer
7-06 to 5-08

+ Consulting with companies on I.C. physical design & EDA tool flows:
- eLCOS (Sunnyvale, CA) tape out of a HDTV LCD controller ASIC;

+ (self) Writing custom presentation and DSP software for Mac OS X (working on Windows) and

+ TA Photographic (Sunnyvale, CA) Design & use of panoramic photography imaging hardware.

Advisory Engineer
1-04 to 7-06

International Business Machines; San J ose, CA;

+ Performed integration (full-chip and FPU levels) for a 10 GHz, (65nm SOI process) PowerPC microprocessor. This was a test chip for experimental circuit techniques, done by a very small team in IBM's Austin Research Labs, and E&TS in San Jose. Tasks included:
- floorplanning both the chip and the FPU unit;
- controlling IC Craftsman place and route tools;
- developing custom routing software (and running it) on the normalizer unit;
- power grid design to work in a very sub-optimal package;
- defining the interface to a C4 flipchip package;
- power analysis; and
- DRC/LVS.

+ Performed integration tasks on a reusable wirebond High-Speed Serial (SERDES) core (90nm bulk CMOS). This job included tools and flows to:
- floorplan potential customer chips;
- define the interface of the core;
- do power grid design & analysis;
- define an inter-organizational flow for image & package customization; and
- "Walk in the shoes of the customer" to make sure end IP is fully usable.

+ Worked at coordinating some network issues between our San Jose "satellite" office and the Rochester MN "home" office;

+ Debugged problems in technology files due to multi-site design process;

+ Development done using SKILL, Virtuoso, Virtuoso Custom Router, and IBM internal tools.

Independent Contract Engineer
8-02 to 12-03

+ Development of Signal Processing Code;

+ Interamco, Inc. (Flint, MI) Manufacturing Engineering & Operations;

Senior Design Engineer
7-01 to 8-02
(left due to layoffs in CAM division)

Micron Technology, Inc.; San Jose, CA:
(Work up to 4-02 done as a consultant with Platinum Consultants, San Jose, CA)
Physical design & verification engineer for Content Addressable Memory Division;

+ Developed and ran a tool flow for full chip power analysis using Synopsis Railmill and Avanti Hercules. The flow was developed to perform IR drop and electro-migration checks on the design from initial planning stages (before all physical information is available) all the way through to final sign off;

+ Identified power related design flaws in the standard cell library;

+ Designed and ran tools to generate an intricate power grid and hookups for a cell phone chip design with very difficult power requirements;

+ Developed system to concentrate physical design data into Cadence DF2 format, and export it properly over to Silicon Ensemble and other LEF/DEF based tools;

+ Debugged problems in technology files due to multi-site design process.

+ Development done using SKILL, Hercules, Perl, Railmill and Silicon Ensemble.


Microprocessor Global Integration Engineer
7-99 to 4-01
(Left due to company shutdown)

HAL Computer Systems, Inc.; Campbell, CA:
Design engineer for a Sparc microprocessor. (It mostly was designed as 1 GHz, single core, 50 million transistor, but at end was 2 GHz, dual core, 75 million transistor);

+ Developed an inductance extraction tool. Physical layout is analyzed to determine not just resistance and capacitance, but also in-line inductance and mutual inductive coupling. The resulting netlist is simulated in SPICE to determine effects on the power grid;

+ Specified (with a co-worker) a dynamic I-R drop and EM analysis flow. This included evaluating, installing, and running Simplex's tools for tasks within this flow;

+ Wrote code to create early "physical prototypes" of blocks to help determine their actual layout, and allow work on the chip integration flow before block-level layout is complete;

+ Developed tools for visualizing flightlines, physical routes, and timing info for global signals;

+ Specified (with a co-worker) a dynamic I-R drop and EM analysis flow. This included evaluating, installing, and running Simplex's tools for tasks within this flow;

+ Developed tools to subdivide an extremely large chip into sections, then perform each section's physical build. This included tools and flows to:
- prepare data for placement, routing, and timing based optimization;
- optimize the route crossings between sections;
- control Silicon Ensemble and IC Craftsman place and route tools;
- re-assemble sections into the global chip;
- physically verify the sections; and
- plot the entire chip or subsections.

+ Development done using SKILL, xCalibre, Perl, custom GDS tools, and EMA (a T-CAD tool);


Senior Member of Technical Staff
7-97 to 11-98

Cadence Design Systems; San Jose, CA:
Developer of commercial tools for physical verification of large, full custom integrated circuits

+ Co-developer of Vampire Short Locator product - an optional module for the Vampire LVS module that allowed users to track down where a short was occurring in their physical design;

+ Program manager for Vampire Short Locator these tasks involved product specification, management approval, training, QA test bench creation, and User Interface design;

+ Organized training for Vampire code base and integrated circuit technology overviews; and

+ Stabilized code base for InQuery product as part of global Dracula R & D team.


Member of Technical Staff
12-96 to 5-97

(Left due to company shutdown)

Exponential Technology; San Jose, CA:
Member of custom-tools CAD staff supporting design of a 533 Mhz PowerPC Microprocessor

+ Improved custom routing and placement tools;

+ Trained in timing-based re-routing of complex layout (Engineering Change Orders); and

+ Interfaced a multi-designer CAD flow to a revision control system (CVS);


Systems Engineer
8-93 to 12-96

Tanner Research; Pasadena, CA:
Developer of commercial tools for design and verification of integrated circuits, multi-chip modules, and micro-machined structures;

+ Initiated and led the company's first expense vs. revenue product analysis;

+ Project leader for device and interconnect recognition from mask-level layout;

+ Project leader for all Macintosh development:
- ported existing DOS, Windows, and UNIX programs to Mac O.S.;
- developed PowerPC optimized versions of programs;
- oversaw manual writing, tech support, and production of Mac programs;

+ Developed user interfaces and an interactive command language for generating layout;

+ Development done cross-platform - on Mac, Windows, Sun, and HP workstations;


Systems Engineer
12-92 to 8-93

Interamco, Inc.; Flint, MI:

+ Networking, database, and manufacturing support for our family business.


Co-op engineering student
6-85 to 7-89

AC Rochester and Delco Electronics Divs. of GM; Flint, MI and Kokomo,IN:

+ Management of production personnel, corporate accounts, and inventory. This included supervising a team of 30 assembly line workers;

+ Worked with customers and suppliers to improve and test automotive electronics;

+ Lead project to create AC's first diagnostic expert system;

+ Designed a production-ready display system using an experimental LCD technology; and

+ Electronics manufacturing, including expert system development, process debugging, control systems design, statistical process & quality control, and industrial engineering.


Other student work

Apple Computer On-campus account manager. Was responsible for identifying and supporting large departmental orders, as well as sales and support to the student body.

MicroSim Corp. Mac programmer. Developed code for remote processing of SPICE jobs.


References Available by request.